`timescale 1ns / 1ps

module divider_tb();

reg cpu_clk_50M;

reg cpu_rst_n;

always #10 cpu_clk_50M = ~cpu_clk_50M;    

reg  [31:0] dividend;
reg [31:0] dividsor;
reg start;


divider divider0(
    .cpu_clk_50M (cpu_clk_50M ),
    .cpu_rst_n   (cpu_rst_n   ),
    .div_start       (start       ),
    .dividend    (dividend    ),
    .dividsor    (dividsor    ),
    .div_end     (div_end),
    .quotient    (quotient    ),
    .remainder   (remainder   )
);


initial begin
		// Initialize Inputs
        cpu_clk_50M = 0;
		cpu_rst_n = 1'b0;
		#200;

		cpu_rst_n = 1'b1;

        start  = 1'b1;
        dividend = 12655;
        dividsor = 855;
        #40;
        start =  1'b0;
        #1500;
        start = 1'b1;
        dividend = 100;
        dividsor = 0;
        #40;
        start = 1'b0; 

		#35_000 $stop;
end


endmodule
